3D integration is regularly mentioned for its potential in decreasing costs, variability and delay in interconnections limiting nowadays IC’s performance. 3D monolithic integration (M3D) is the only option enabling a full use of the third dimension at the cell scale thanks to its high alignment precision.
At the CMOS cell level 3D monolithic integration offers the unique additional benefit to allow for an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers suppressing thus lots of technological challenges.
Within this context 3D monolithic integration appears as an opportunity both for next-generation semiconductors over Si integration.
Our research is aimed to develop printing-based M3D integration of various electronic circuits on Si or Non-Si CMOS.